Autonomous Relay Finite State Machine (FSM)
In modern residential and industrial grids, myriad "dumb" appliances—heavy centrifugal induction pumps, fan matrices, continuous DC motors—lack localized timeout circuitry. Without internal temporal constraints, they rely exclusively on manual circuit interrupts, often resulting in wasteful energy telemetry loops (e.g., fluid reservoirs overflowing past total capacity integers). The Hello Digital Timer establishes a programmatic intervention layer utilizing an optical isolation Solid State Relay (SSR) protocol. The system autonomously disrupts the primary payload pipeline entirely based on localized time-variable parameters mapped directly through the UNO architecture.
Variable Calibration via ADC Multiplexing
Rather than strictly embedding timeout limits purely in code limits, we architected a physical tuning interface capitalizing on voltage division.
- A 10K Ohm rotary potentiometer drives a localized voltage drop vector mapped natively onto Analog Pin
A1. The ADC parses this scalar and mathematically translates the raw0-1023integer into a usableMinutemetric controlling the overall state duration variable. - A secondary parallel potentiometer channels onto Analog Pin
A2, generating a separate integer variable dedicated only to computing the secondary alarm buzzer delay threshold (scaled directly intoseconds). - A tertiary trim-pot interfaces mechanically with the 16x2 alphanumeric LCD logic, shifting liquid crystal V0 contrast curves.
Upon executing system initiation via the principal interrupt Pushbutton, the CPU executes the primary loop: The SSR triggers HIGH, feeding mains load AC vectors to external lamps/fans. The LCD iterates downward systematically per temporal second. Upon hitting absolute null (0), the logic loop flips the SSR boolean to LOW, terminating energy routing. Simultaneously, the acoustic array (Piezo Buzzer) receives a PWM payload alerting operations failure until its specific temporal cap terminates completely.