If you have arrived at this article by random means and not via its starting point, then you may find that it may not make much sense. This is because this article is one of several (six) tutorials to aid and assist in understanding the use of the ez_SIPO8_lib library in managing and controlling Serial-in/Parallel-out ICs (SIPOs) shift registers, for example 74HC595 chips.
If you wish to link to the start of the tutorial then please follow this link (Tutorial Start), otherwise, please read on...
Q&As - What is/How Can I/How Do I...
A tutorial to consolidate understanding and use of the ez Serial-in/Parallel-out IC Library (ez_SIPO8_lib) - Tutorial 6, Questions & Answers. If you wish to link to the tutorial starting article then follow this link: Tutorial Start.You can access and download the User Guide, Crib Sheet and the original ez_SIPO8_lib article by following these links below:- ez_SIPO8_lib User Guide- ez_SIPO8_lib Crib Sheet- Read the full ez_SIPO8_lib articleIntroduction to the Tutorial
In this tutorial we will deal with a number of Questions & Answers (Q&As), looking at what is going on behind the scenes and how we can use some of the SIPO8 library’s inner features to good effect.
Project Perspective
Shift Registers - Tutorial 6, Q&As is a sophisticated exploration of digital technology and logical-cascading interaction. By focusing on the essential building blocks—the 74HC595 shift-storage register array and your multi-bank ez_SIPO8 software logic—you'll learn how to communicate and synchronize high-density I/O tasks using a specialized software logic and robust manual setup.
Technical Implementation: Serial-to-Parallel and Bank Mapping
The project reveals the hidden layers of simple data-to-pin interaction:
- Identification layer: The 74HC595 ICs act as a high-resolution binary interface, measuring each point of the clock/data pulses via the serial bus.
- Conversion layer: The system uses a high-speed SPI-like protocol (Data, Clock, Latch) to receive high-speed bitstreams and coordinate mission-critical sensing tasks.
- Expansion Interface layer: Eight Cascaded 74HC595 Registers provide high-definition visual feedback for each I/O status check (e.g., 64 independent outputs).
- Processing Logic: The Arduino code follows a "bit-dispatch" (or bank-dispatch) strategy: it interprets the library commands and matches pin states to provide safe and rhythmic digital control.
- Communication Dialogue Loop: Pin status strings are sent rhythmically to the Serial Monitor during initial calibration to coordinate status.
Objectives
We shall assume that if you have covered previous tutorials you will already have setup a test harness comprising a single SIPO IC and connected LEDs, but if not and you wish to practise some of the features covered by this tutorial then setup the components as outlined in a previous Tutorial, eg see Tutorial 1, Absolute Addressing.
In this tutorial we shall explore some obvious and less so obvious questions and provide, hopefully, helpful answers.
Q1. What is the virtual array pool of output pins?
A1. The SIPO8 library will create and reserve space for every SIPO IC output pin you request when you instantiate the library’s class. This is determined by the first parameter of the class instantiation statement, e.g. SPIO8 my_SIPOs(4, 0), here the request is to create a virtual SIPO output pin environment of 4 x single 8-bit SPIO ICs, or 4 x 8 = 32 output pins.
The entire virtual set of SIPO output pins are referred to as the virtual array or array pool, with an address range from 0 to the (8 x number of SIPO ICs) – 1. In the above example the address range is 0 to 31.
It is important to understand that, once created, the virtual output pin array is not yet addressable. This is because that the library does not yet know how these virtual output pins are to be associated with/linked to the physical world, i.e. physical SIPO ICs. This cannot happen until we allocate the array pool to one or more banks. See question 2.
Q2. How do I link the virtual output pins in the array pool to physical SIPO ICs?
Having defined and created our virtual array pool by instantiating the library's class, we now need to 'chop it up'/allocate it into 'banks' of grouped output pins using the create_bank function. A bank will:
- comprise a unique set of virtual output pins allocated from the virtual array pool
- map a consecutive and contiguous absolute address range of virtual output pins into the bank, thereby allowing the these outputs to be addressed relatively to the bank in which they exist - the first output port address of every bank is 0, representing the least significant bit of the bank's SIPO
- define the 3-wire digital microcontroller pins used to drive the bank
- make the bank’s associated output pins active and therefore addressable, absolutely and relatively (see question 3)
For example, using our example above (SPIO8 my_SIPOs(4, 0)), we wish split up our 32 virtual output pins into 2 banks - 1 bank of 8 output pins and the other bank of the remaining 24 output pins, and allocate these to microcontroller digital pins 3, 4, 5 and A0, A1, A2 respectively. The banks are created using the create_bank function so:
bank1_id = my_SIPOs.create_bank(3, 4, 5, 1); // 8 outputs
bank2_id = my_SIPOs.create_bank(A0, A1, A2, 3); //24 outputs
The first create_bank call allocates array pool pins 0–7 to the first bank (bank1_id) and makes the associated output pins active and addressable (absolutely and relatively). The second create_bank allocates array pool output pins 8–31 to the second bank (bank2_id) and makes the associated output pins active and addressable.
Now the array pool is fully allocated to our banks and all output pins active we can address them in two ways – by absolute addressing and by relative addressing. See question 3.
As an aside, if we tried to call the create_bank function again we would obtain an error, as all instantiation declared SIPOs have been allocated from the array pool - we requested 4 and we allocated 4 (1 + 3).
Q3. What is the difference between absolute addressing and relative addressing?
A3. The answer is very simple:
Absolute addresses relate only to the active output pins in the virtual array pool with an inclusive address range from 0 to (the total number of output pins) - 1 in the array pool. There are few functions (but sufficient) that use absolute addressing, these are:
set_all_array_pins(status)implicit absolute addressing
invert_all_array_pins()implicit absolute addressing
set_array_pin(pin_address)explicit absolute addressing
invert_array_pin(pin_address)explicit absolute addressing
read_array_pin(pin_address)explicit absolute addressing
xfer_array(LSBFIRST_or_MSBFIRST)implicit absolute addressing
where
pin_address is the absolute address of the pin in the active array pool, i.e. an address range from 0 to the (8 x total number of defined and active SIPO ICs) – 1. In the above example, the absolute address range is from 0–31 inclusive. (See the User Guide for a full description of each of these functions.)
Relative addresses relate only to the active output pins in a bank with an inclusive address range from 0 to (the number of output pins in a bank) - 1. There are many bank related functions that use relative addressing, these are:
set_bank_pin(bank_id,pin_address, status)explicit relative addressing
invert_bank_pin(bank_id,pin_address)explicit relative addressing
read_bank_pin(bank_id,pin_address)explicit relative addressing
set_bank(bank_id,status)implicit relative addressing
set_banks(from_bank,to_bank, status)implicit relative addressing
set_banks(status)implicit relative addressing
invert_bank(bank_id)implicit relative addressing
invert_banks(from_bank,to_bank)implicit relative addressing
invert_banks()implicit relative addressing
set_bank_SIPO(bank_id,SIPO_num, SIPO_value)implicit relative addressing
invert_bank_SIPO(bank_id,SIPO_num)implicit relative addressing
read_bank_SIPO(bank_id,SIPO_num)implicit relative addressing
xfer_bank(bank_id,LSBFIRST_or_MSBFIRST)implicit relative addressing
xfer_banks(bank_from,bank_to, LSBFIRST_or_MSBFIRST)implicit relative addressing
xfer_banks(LSBFIRST_or_MSBFIRST)implicit relative addressing
where
pin_address is the relative address of the pin in the bank, i.e. an address range from 0 to (number of output pins in the bank) – 1.
SIPO_num is the relative address of an 8-bit SIPO define by the bank, i.e. ranges from 0 to (number of SIPOs defined for the bank) – 1.
In the above example, the array pool of size 4 x SIPO ICs is split into two separate banks, one bank with 1 x SIPO IC and the other with 3 x SIPO ICs, the respective addressing ranges are:
array pool, absolute address range: 0–31
bank1_id relative address output pin range: 0-7, relative SIPO byte range: 0-0
bank2_id relative address output pin range:0–23, relative SIPO byte range: 0-2
(See the User Guide for a full description of each of these functions.)
Q4.How do I know how many virtual SIPO output pins there are in the array pool?
A4. The library provides a number of user accessible variables that are helpful in decision support and control. In this particular case, the library variable to use is max_pins*,and you would use it by prefixing it with the name you gave for the SIPO8 class when you instantiated it. For example, if you named your class ‘my_SIPOs’ then the use would be my_SIPOs.max_pins.
Be aware that this value is the total number of output pins defined at library class instantiation - it is not the number of active output pins, see question 5.
Q5. How do I know how many virtual active output SIPO pins there are in the array pool?
A5. Again, we would use a library variable, in this instance the library variable num_active_pins*, and you would use it by prefixing it with the name you gave for the SIPO8 class when you instantiated it. For example, my_SIPOs.num_active_pins.
* Note that there is a distinction to be made between how many SIPO pins an array pool is sized for (max_pins) and the number of active pins (num_active_pins) in an array. When the SIPO8 class is instantiated, the array pin pool is created